// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  vpc_cvdr_reg_nmanager_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2013/3/10
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/19 14:37:49 Create file
// ******************************************************************************

#ifndef __VPC_CVDR_REG_NMANAGER_REG_OFFSET_FIELD_H__
#define __VPC_CVDR_REG_NMANAGER_REG_OFFSET_FIELD_H__

#define VPC_CVDR_REG_NMANAGER_MAX_AXIWRITE_ID_LEN          5
#define VPC_CVDR_REG_NMANAGER_MAX_AXIWRITE_ID_OFFSET       24
#define VPC_CVDR_REG_NMANAGER_MAX_AXIREAD_ID_LEN           5
#define VPC_CVDR_REG_NMANAGER_MAX_AXIREAD_ID_OFFSET        16
#define VPC_CVDR_REG_NMANAGER_DU_THRESHOLD_REACHED_LEN     8
#define VPC_CVDR_REG_NMANAGER_DU_THRESHOLD_REACHED_OFFSET  8
#define VPC_CVDR_REG_NMANAGER_AXIWRITE_DU_THRESHOLD_LEN    6
#define VPC_CVDR_REG_NMANAGER_AXIWRITE_DU_THRESHOLD_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_RD_PEAK_EN_LEN    1
#define VPC_CVDR_REG_NMANAGER_RD_PEAK_EN_OFFSET 8
#define VPC_CVDR_REG_NMANAGER_WR_PEAK_EN_LEN    1
#define VPC_CVDR_REG_NMANAGER_WR_PEAK_EN_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_RD_PEAK_LEN    8
#define VPC_CVDR_REG_NMANAGER_RD_PEAK_OFFSET 8
#define VPC_CVDR_REG_NMANAGER_WR_PEAK_LEN    8
#define VPC_CVDR_REG_NMANAGER_WR_PEAK_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_WR_QOS_SR_LEN                    2
#define VPC_CVDR_REG_NMANAGER_WR_QOS_SR_OFFSET                 30
#define VPC_CVDR_REG_NMANAGER_WR_QOS_MAX_LEN                   2
#define VPC_CVDR_REG_NMANAGER_WR_QOS_MAX_OFFSET                28
#define VPC_CVDR_REG_NMANAGER_WR_QOS_MIN_LEN                   2
#define VPC_CVDR_REG_NMANAGER_WR_QOS_MIN_OFFSET                26
#define VPC_CVDR_REG_NMANAGER_WR_QOS_THRESHOLD_11_START_LEN    4
#define VPC_CVDR_REG_NMANAGER_WR_QOS_THRESHOLD_11_START_OFFSET 20
#define VPC_CVDR_REG_NMANAGER_WR_QOS_THRESHOLD_11_STOP_LEN     4
#define VPC_CVDR_REG_NMANAGER_WR_QOS_THRESHOLD_11_STOP_OFFSET  16
#define VPC_CVDR_REG_NMANAGER_WR_QOS_THRESHOLD_10_START_LEN    4
#define VPC_CVDR_REG_NMANAGER_WR_QOS_THRESHOLD_10_START_OFFSET 12
#define VPC_CVDR_REG_NMANAGER_WR_QOS_THRESHOLD_10_STOP_LEN     4
#define VPC_CVDR_REG_NMANAGER_WR_QOS_THRESHOLD_10_STOP_OFFSET  8
#define VPC_CVDR_REG_NMANAGER_WR_QOS_THRESHOLD_01_START_LEN    4
#define VPC_CVDR_REG_NMANAGER_WR_QOS_THRESHOLD_01_START_OFFSET 4
#define VPC_CVDR_REG_NMANAGER_WR_QOS_THRESHOLD_01_STOP_LEN     4
#define VPC_CVDR_REG_NMANAGER_WR_QOS_THRESHOLD_01_STOP_OFFSET  0

#define VPC_CVDR_REG_NMANAGER_RD_QOS_SR_LEN                    2
#define VPC_CVDR_REG_NMANAGER_RD_QOS_SR_OFFSET                 30
#define VPC_CVDR_REG_NMANAGER_RD_QOS_MAX_LEN                   2
#define VPC_CVDR_REG_NMANAGER_RD_QOS_MAX_OFFSET                28
#define VPC_CVDR_REG_NMANAGER_RD_QOS_MIN_LEN                   2
#define VPC_CVDR_REG_NMANAGER_RD_QOS_MIN_OFFSET                26
#define VPC_CVDR_REG_NMANAGER_RD_QOS_THRESHOLD_11_START_LEN    4
#define VPC_CVDR_REG_NMANAGER_RD_QOS_THRESHOLD_11_START_OFFSET 20
#define VPC_CVDR_REG_NMANAGER_RD_QOS_THRESHOLD_11_STOP_LEN     4
#define VPC_CVDR_REG_NMANAGER_RD_QOS_THRESHOLD_11_STOP_OFFSET  16
#define VPC_CVDR_REG_NMANAGER_RD_QOS_THRESHOLD_10_START_LEN    4
#define VPC_CVDR_REG_NMANAGER_RD_QOS_THRESHOLD_10_START_OFFSET 12
#define VPC_CVDR_REG_NMANAGER_RD_QOS_THRESHOLD_10_STOP_LEN     4
#define VPC_CVDR_REG_NMANAGER_RD_QOS_THRESHOLD_10_STOP_OFFSET  8
#define VPC_CVDR_REG_NMANAGER_RD_QOS_THRESHOLD_01_START_LEN    4
#define VPC_CVDR_REG_NMANAGER_RD_QOS_THRESHOLD_01_START_OFFSET 4
#define VPC_CVDR_REG_NMANAGER_RD_QOS_THRESHOLD_01_STOP_LEN     4
#define VPC_CVDR_REG_NMANAGER_RD_QOS_THRESHOLD_01_STOP_OFFSET  0

#define VPC_CVDR_REG_NMANAGER_FORCE_CFG_CLK_ON_LEN       1
#define VPC_CVDR_REG_NMANAGER_FORCE_CFG_CLK_ON_OFFSET    8
#define VPC_CVDR_REG_NMANAGER_FORCE_DU_WR_CLK_ON_LEN     1
#define VPC_CVDR_REG_NMANAGER_FORCE_DU_WR_CLK_ON_OFFSET  7
#define VPC_CVDR_REG_NMANAGER_FORCE_DU_RD_CLK_ON_LEN     1
#define VPC_CVDR_REG_NMANAGER_FORCE_DU_RD_CLK_ON_OFFSET  6
#define VPC_CVDR_REG_NMANAGER_FORCE_AXI_WR_CLK_ON_LEN    1
#define VPC_CVDR_REG_NMANAGER_FORCE_AXI_WR_CLK_ON_OFFSET 5
#define VPC_CVDR_REG_NMANAGER_FORCE_AXI_RD_CLK_ON_LEN    1
#define VPC_CVDR_REG_NMANAGER_FORCE_AXI_RD_CLK_ON_OFFSET 4
#define VPC_CVDR_REG_NMANAGER_FORCE_NRWR_CLK_ON_LEN      1
#define VPC_CVDR_REG_NMANAGER_FORCE_NRWR_CLK_ON_OFFSET   3
#define VPC_CVDR_REG_NMANAGER_FORCE_NRRD_CLK_ON_LEN      1
#define VPC_CVDR_REG_NMANAGER_FORCE_NRRD_CLK_ON_OFFSET   2
#define VPC_CVDR_REG_NMANAGER_FORCE_VPWR_CLK_ON_LEN      1
#define VPC_CVDR_REG_NMANAGER_FORCE_VPWR_CLK_ON_OFFSET   1
#define VPC_CVDR_REG_NMANAGER_FORCE_VPRD_CLK_ON_LEN      1
#define VPC_CVDR_REG_NMANAGER_FORCE_VPRD_CLK_ON_OFFSET   0

#define VPC_CVDR_REG_NMANAGER_OTHER_RO_LEN    32
#define VPC_CVDR_REG_NMANAGER_OTHER_RO_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_OTHER_RW_LEN    32
#define VPC_CVDR_REG_NMANAGER_OTHER_RW_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_VPWR_LAST_PAGE_0_LEN          19
#define VPC_CVDR_REG_NMANAGER_VPWR_LAST_PAGE_0_OFFSET       13
#define VPC_CVDR_REG_NMANAGER_VPWR_PIXEL_EXPANSION_0_LEN    1
#define VPC_CVDR_REG_NMANAGER_VPWR_PIXEL_EXPANSION_0_OFFSET 4
#define VPC_CVDR_REG_NMANAGER_VPWR_PIXEL_FORMAT_0_LEN       4
#define VPC_CVDR_REG_NMANAGER_VPWR_PIXEL_FORMAT_0_OFFSET    0

#define VPC_CVDR_REG_NMANAGER_VPWR_ADDRESS_FRAME_START_0_LEN    30
#define VPC_CVDR_REG_NMANAGER_VPWR_ADDRESS_FRAME_START_0_OFFSET 2

#define VPC_CVDR_REG_NMANAGER_VPWR_LINE_WRAP_0_LEN      14
#define VPC_CVDR_REG_NMANAGER_VPWR_LINE_WRAP_0_OFFSET   15
#define VPC_CVDR_REG_NMANAGER_VPWR_LINE_STRIDE_0_LEN    10
#define VPC_CVDR_REG_NMANAGER_VPWR_LINE_STRIDE_0_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_VPWR_PREFETCH_BYPASS_0_LEN                      1
#define VPC_CVDR_REG_NMANAGER_VPWR_PREFETCH_BYPASS_0_OFFSET                   31
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_0_LEN                                1
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_0_OFFSET                             25
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_OK_0_LEN                             1
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_OK_0_OFFSET                          24
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_PRESSURE_0_LEN                1
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_PRESSURE_0_OFFSET             18
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_FLUX_CTRL_0_LEN               1
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_FLUX_CTRL_0_OFFSET            17
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_DU_THRESHOLD_REACHED_0_LEN    1
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_DU_THRESHOLD_REACHED_0_OFFSET 16

#define VPC_CVDR_REG_NMANAGER_VPWR_LAST_PAGE_1_LEN          19
#define VPC_CVDR_REG_NMANAGER_VPWR_LAST_PAGE_1_OFFSET       13
#define VPC_CVDR_REG_NMANAGER_VPWR_PIXEL_EXPANSION_1_LEN    1
#define VPC_CVDR_REG_NMANAGER_VPWR_PIXEL_EXPANSION_1_OFFSET 4
#define VPC_CVDR_REG_NMANAGER_VPWR_PIXEL_FORMAT_1_LEN       4
#define VPC_CVDR_REG_NMANAGER_VPWR_PIXEL_FORMAT_1_OFFSET    0

#define VPC_CVDR_REG_NMANAGER_VPWR_ADDRESS_FRAME_START_1_LEN    30
#define VPC_CVDR_REG_NMANAGER_VPWR_ADDRESS_FRAME_START_1_OFFSET 2

#define VPC_CVDR_REG_NMANAGER_VPWR_LINE_WRAP_1_LEN      14
#define VPC_CVDR_REG_NMANAGER_VPWR_LINE_WRAP_1_OFFSET   15
#define VPC_CVDR_REG_NMANAGER_VPWR_LINE_STRIDE_1_LEN    10
#define VPC_CVDR_REG_NMANAGER_VPWR_LINE_STRIDE_1_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_VPWR_PREFETCH_BYPASS_1_LEN                      1
#define VPC_CVDR_REG_NMANAGER_VPWR_PREFETCH_BYPASS_1_OFFSET                   31
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_1_LEN                                1
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_1_OFFSET                             25
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_OK_1_LEN                             1
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_OK_1_OFFSET                          24
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_PRESSURE_1_LEN                1
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_PRESSURE_1_OFFSET             18
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_FLUX_CTRL_1_LEN               1
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_FLUX_CTRL_1_OFFSET            17
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_DU_THRESHOLD_REACHED_1_LEN    1
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_DU_THRESHOLD_REACHED_1_OFFSET 16

#define VPC_CVDR_REG_NMANAGER_VPWR_LAST_PAGE_2_LEN          19
#define VPC_CVDR_REG_NMANAGER_VPWR_LAST_PAGE_2_OFFSET       13
#define VPC_CVDR_REG_NMANAGER_VPWR_PIXEL_EXPANSION_2_LEN    1
#define VPC_CVDR_REG_NMANAGER_VPWR_PIXEL_EXPANSION_2_OFFSET 4
#define VPC_CVDR_REG_NMANAGER_VPWR_PIXEL_FORMAT_2_LEN       4
#define VPC_CVDR_REG_NMANAGER_VPWR_PIXEL_FORMAT_2_OFFSET    0

#define VPC_CVDR_REG_NMANAGER_VPWR_ADDRESS_FRAME_START_2_LEN    30
#define VPC_CVDR_REG_NMANAGER_VPWR_ADDRESS_FRAME_START_2_OFFSET 2

#define VPC_CVDR_REG_NMANAGER_VPWR_LINE_WRAP_2_LEN      14
#define VPC_CVDR_REG_NMANAGER_VPWR_LINE_WRAP_2_OFFSET   15
#define VPC_CVDR_REG_NMANAGER_VPWR_LINE_STRIDE_2_LEN    10
#define VPC_CVDR_REG_NMANAGER_VPWR_LINE_STRIDE_2_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_VPWR_PREFETCH_BYPASS_2_LEN                      1
#define VPC_CVDR_REG_NMANAGER_VPWR_PREFETCH_BYPASS_2_OFFSET                   31
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_2_LEN                                1
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_2_OFFSET                             25
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_OK_2_LEN                             1
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_OK_2_OFFSET                          24
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_PRESSURE_2_LEN                1
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_PRESSURE_2_OFFSET             18
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_FLUX_CTRL_2_LEN               1
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_FLUX_CTRL_2_OFFSET            17
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_DU_THRESHOLD_REACHED_2_LEN    1
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_DU_THRESHOLD_REACHED_2_OFFSET 16

#define VPC_CVDR_REG_NMANAGER_VPWR_LAST_PAGE_3_LEN          19
#define VPC_CVDR_REG_NMANAGER_VPWR_LAST_PAGE_3_OFFSET       13
#define VPC_CVDR_REG_NMANAGER_VPWR_PIXEL_EXPANSION_3_LEN    1
#define VPC_CVDR_REG_NMANAGER_VPWR_PIXEL_EXPANSION_3_OFFSET 4
#define VPC_CVDR_REG_NMANAGER_VPWR_PIXEL_FORMAT_3_LEN       4
#define VPC_CVDR_REG_NMANAGER_VPWR_PIXEL_FORMAT_3_OFFSET    0

#define VPC_CVDR_REG_NMANAGER_VPWR_ADDRESS_FRAME_START_3_LEN    30
#define VPC_CVDR_REG_NMANAGER_VPWR_ADDRESS_FRAME_START_3_OFFSET 2

#define VPC_CVDR_REG_NMANAGER_VPWR_LINE_WRAP_3_LEN      14
#define VPC_CVDR_REG_NMANAGER_VPWR_LINE_WRAP_3_OFFSET   15
#define VPC_CVDR_REG_NMANAGER_VPWR_LINE_STRIDE_3_LEN    10
#define VPC_CVDR_REG_NMANAGER_VPWR_LINE_STRIDE_3_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_VPWR_PREFETCH_BYPASS_3_LEN                      1
#define VPC_CVDR_REG_NMANAGER_VPWR_PREFETCH_BYPASS_3_OFFSET                   31
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_3_LEN                                1
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_3_OFFSET                             25
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_OK_3_LEN                             1
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_OK_3_OFFSET                          24
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_PRESSURE_3_LEN                1
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_PRESSURE_3_OFFSET             18
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_FLUX_CTRL_3_LEN               1
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_FLUX_CTRL_3_OFFSET            17
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_DU_THRESHOLD_REACHED_3_LEN    1
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_DU_THRESHOLD_REACHED_3_OFFSET 16

#define VPC_CVDR_REG_NMANAGER_VPWR_LAST_PAGE_4_LEN          19
#define VPC_CVDR_REG_NMANAGER_VPWR_LAST_PAGE_4_OFFSET       13
#define VPC_CVDR_REG_NMANAGER_VPWR_PIXEL_EXPANSION_4_LEN    1
#define VPC_CVDR_REG_NMANAGER_VPWR_PIXEL_EXPANSION_4_OFFSET 4
#define VPC_CVDR_REG_NMANAGER_VPWR_PIXEL_FORMAT_4_LEN       4
#define VPC_CVDR_REG_NMANAGER_VPWR_PIXEL_FORMAT_4_OFFSET    0

#define VPC_CVDR_REG_NMANAGER_VPWR_ADDRESS_FRAME_START_4_LEN    30
#define VPC_CVDR_REG_NMANAGER_VPWR_ADDRESS_FRAME_START_4_OFFSET 2

#define VPC_CVDR_REG_NMANAGER_VPWR_LINE_WRAP_4_LEN      14
#define VPC_CVDR_REG_NMANAGER_VPWR_LINE_WRAP_4_OFFSET   15
#define VPC_CVDR_REG_NMANAGER_VPWR_LINE_STRIDE_4_LEN    10
#define VPC_CVDR_REG_NMANAGER_VPWR_LINE_STRIDE_4_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_VPWR_PREFETCH_BYPASS_4_LEN                      1
#define VPC_CVDR_REG_NMANAGER_VPWR_PREFETCH_BYPASS_4_OFFSET                   31
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_4_LEN                                1
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_4_OFFSET                             25
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_OK_4_LEN                             1
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_OK_4_OFFSET                          24
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_PRESSURE_4_LEN                1
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_PRESSURE_4_OFFSET             18
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_FLUX_CTRL_4_LEN               1
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_FLUX_CTRL_4_OFFSET            17
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_DU_THRESHOLD_REACHED_4_LEN    1
#define VPC_CVDR_REG_NMANAGER_VP_WR_STOP_ENABLE_DU_THRESHOLD_REACHED_4_OFFSET 16

#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_RELOAD_0_LEN    4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_RELOAD_0_OFFSET 24
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_3_0_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_3_0_OFFSET      12
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_2_0_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_2_0_OFFSET      8
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_1_0_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_1_0_OFFSET      4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_0_0_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_0_0_OFFSET      0

#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_RELOAD_1_LEN    4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_RELOAD_1_OFFSET 24
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_3_1_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_3_1_OFFSET      12
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_2_1_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_2_1_OFFSET      8
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_1_1_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_1_1_OFFSET      4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_0_1_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_0_1_OFFSET      0

#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_RELOAD_2_LEN    4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_RELOAD_2_OFFSET 24
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_3_2_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_3_2_OFFSET      12
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_2_2_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_2_2_OFFSET      8
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_1_2_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_1_2_OFFSET      4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_0_2_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_0_2_OFFSET      0

#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_RELOAD_3_LEN    4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_RELOAD_3_OFFSET 24
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_3_3_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_3_3_OFFSET      12
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_2_3_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_2_3_OFFSET      8
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_1_3_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_1_3_OFFSET      4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_0_3_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_0_3_OFFSET      0

#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_RELOAD_4_LEN    4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_RELOAD_4_OFFSET 24
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_3_4_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_3_4_OFFSET      12
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_2_4_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_2_4_OFFSET      8
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_1_4_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_1_4_OFFSET      4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_0_4_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPWR_ACCESS_LIMITER_0_4_OFFSET      0

#define VPC_CVDR_REG_NMANAGER_VPRD_LAST_PAGE_0_LEN          19
#define VPC_CVDR_REG_NMANAGER_VPRD_LAST_PAGE_0_OFFSET       13
#define VPC_CVDR_REG_NMANAGER_VPRD_ALLOCATED_DU_0_LEN       5
#define VPC_CVDR_REG_NMANAGER_VPRD_ALLOCATED_DU_0_OFFSET    5
#define VPC_CVDR_REG_NMANAGER_VPRD_PIXEL_EXPANSION_0_LEN    1
#define VPC_CVDR_REG_NMANAGER_VPRD_PIXEL_EXPANSION_0_OFFSET 4
#define VPC_CVDR_REG_NMANAGER_VPRD_PIXEL_FORMAT_0_LEN       4
#define VPC_CVDR_REG_NMANAGER_VPRD_PIXEL_FORMAT_0_OFFSET    0

#define VPC_CVDR_REG_NMANAGER_VPRD_HORIZONTAL_BLANKING_0_LEN    8
#define VPC_CVDR_REG_NMANAGER_VPRD_HORIZONTAL_BLANKING_0_OFFSET 16
#define VPC_CVDR_REG_NMANAGER_VPRD_LINE_SIZE_0_LEN              13
#define VPC_CVDR_REG_NMANAGER_VPRD_LINE_SIZE_0_OFFSET           0

#define VPC_CVDR_REG_NMANAGER_VPRD_VERTICAL_BLANKING_0_LEN    8
#define VPC_CVDR_REG_NMANAGER_VPRD_VERTICAL_BLANKING_0_OFFSET 16
#define VPC_CVDR_REG_NMANAGER_VPRD_FRAME_SIZE_0_LEN           13
#define VPC_CVDR_REG_NMANAGER_VPRD_FRAME_SIZE_0_OFFSET        0

#define VPC_CVDR_REG_NMANAGER_VPRD_AXI_FRAME_START_0_LEN    30
#define VPC_CVDR_REG_NMANAGER_VPRD_AXI_FRAME_START_0_OFFSET 2

#define VPC_CVDR_REG_NMANAGER_VPRD_LINE_WRAP_0_LEN      13
#define VPC_CVDR_REG_NMANAGER_VPRD_LINE_WRAP_0_OFFSET   16
#define VPC_CVDR_REG_NMANAGER_VPRD_LINE_STRIDE_0_LEN    10
#define VPC_CVDR_REG_NMANAGER_VPRD_LINE_STRIDE_0_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_VPRD_PREFETCH_BYPASS_0_LEN                      1
#define VPC_CVDR_REG_NMANAGER_VPRD_PREFETCH_BYPASS_0_OFFSET                   31
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_0_LEN                                1
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_0_OFFSET                             25
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_OK_0_LEN                             1
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_OK_0_OFFSET                          24
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_ENABLE_PRESSURE_0_LEN                1
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_ENABLE_PRESSURE_0_OFFSET             18
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_ENABLE_FLUX_CTRL_0_LEN               1
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_ENABLE_FLUX_CTRL_0_OFFSET            17
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_ENABLE_DU_THRESHOLD_REACHED_0_LEN    1
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_ENABLE_DU_THRESHOLD_REACHED_0_OFFSET 16

#define VPC_CVDR_REG_NMANAGER_VP_RD_DEBUG_0_LEN    32
#define VPC_CVDR_REG_NMANAGER_VP_RD_DEBUG_0_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_VPRD_LAST_PAGE_1_LEN          19
#define VPC_CVDR_REG_NMANAGER_VPRD_LAST_PAGE_1_OFFSET       13
#define VPC_CVDR_REG_NMANAGER_VPRD_ALLOCATED_DU_1_LEN       5
#define VPC_CVDR_REG_NMANAGER_VPRD_ALLOCATED_DU_1_OFFSET    5
#define VPC_CVDR_REG_NMANAGER_VPRD_PIXEL_EXPANSION_1_LEN    1
#define VPC_CVDR_REG_NMANAGER_VPRD_PIXEL_EXPANSION_1_OFFSET 4
#define VPC_CVDR_REG_NMANAGER_VPRD_PIXEL_FORMAT_1_LEN       4
#define VPC_CVDR_REG_NMANAGER_VPRD_PIXEL_FORMAT_1_OFFSET    0

#define VPC_CVDR_REG_NMANAGER_VPRD_HORIZONTAL_BLANKING_1_LEN    8
#define VPC_CVDR_REG_NMANAGER_VPRD_HORIZONTAL_BLANKING_1_OFFSET 16
#define VPC_CVDR_REG_NMANAGER_VPRD_LINE_SIZE_1_LEN              13
#define VPC_CVDR_REG_NMANAGER_VPRD_LINE_SIZE_1_OFFSET           0

#define VPC_CVDR_REG_NMANAGER_VPRD_VERTICAL_BLANKING_1_LEN    8
#define VPC_CVDR_REG_NMANAGER_VPRD_VERTICAL_BLANKING_1_OFFSET 16
#define VPC_CVDR_REG_NMANAGER_VPRD_FRAME_SIZE_1_LEN           13
#define VPC_CVDR_REG_NMANAGER_VPRD_FRAME_SIZE_1_OFFSET        0

#define VPC_CVDR_REG_NMANAGER_VPRD_AXI_FRAME_START_1_LEN    30
#define VPC_CVDR_REG_NMANAGER_VPRD_AXI_FRAME_START_1_OFFSET 2

#define VPC_CVDR_REG_NMANAGER_VPRD_LINE_WRAP_1_LEN      13
#define VPC_CVDR_REG_NMANAGER_VPRD_LINE_WRAP_1_OFFSET   16
#define VPC_CVDR_REG_NMANAGER_VPRD_LINE_STRIDE_1_LEN    10
#define VPC_CVDR_REG_NMANAGER_VPRD_LINE_STRIDE_1_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_VPRD_PREFETCH_BYPASS_1_LEN                      1
#define VPC_CVDR_REG_NMANAGER_VPRD_PREFETCH_BYPASS_1_OFFSET                   31
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_1_LEN                                1
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_1_OFFSET                             25
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_OK_1_LEN                             1
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_OK_1_OFFSET                          24
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_ENABLE_PRESSURE_1_LEN                1
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_ENABLE_PRESSURE_1_OFFSET             18
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_ENABLE_FLUX_CTRL_1_LEN               1
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_ENABLE_FLUX_CTRL_1_OFFSET            17
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_ENABLE_DU_THRESHOLD_REACHED_1_LEN    1
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_ENABLE_DU_THRESHOLD_REACHED_1_OFFSET 16

#define VPC_CVDR_REG_NMANAGER_VP_RD_DEBUG_1_LEN    32
#define VPC_CVDR_REG_NMANAGER_VP_RD_DEBUG_1_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_VPRD_LAST_PAGE_2_LEN          19
#define VPC_CVDR_REG_NMANAGER_VPRD_LAST_PAGE_2_OFFSET       13
#define VPC_CVDR_REG_NMANAGER_VPRD_ALLOCATED_DU_2_LEN       5
#define VPC_CVDR_REG_NMANAGER_VPRD_ALLOCATED_DU_2_OFFSET    5
#define VPC_CVDR_REG_NMANAGER_VPRD_PIXEL_EXPANSION_2_LEN    1
#define VPC_CVDR_REG_NMANAGER_VPRD_PIXEL_EXPANSION_2_OFFSET 4
#define VPC_CVDR_REG_NMANAGER_VPRD_PIXEL_FORMAT_2_LEN       4
#define VPC_CVDR_REG_NMANAGER_VPRD_PIXEL_FORMAT_2_OFFSET    0

#define VPC_CVDR_REG_NMANAGER_VPRD_HORIZONTAL_BLANKING_2_LEN    8
#define VPC_CVDR_REG_NMANAGER_VPRD_HORIZONTAL_BLANKING_2_OFFSET 16
#define VPC_CVDR_REG_NMANAGER_VPRD_LINE_SIZE_2_LEN              13
#define VPC_CVDR_REG_NMANAGER_VPRD_LINE_SIZE_2_OFFSET           0

#define VPC_CVDR_REG_NMANAGER_VPRD_VERTICAL_BLANKING_2_LEN    8
#define VPC_CVDR_REG_NMANAGER_VPRD_VERTICAL_BLANKING_2_OFFSET 16
#define VPC_CVDR_REG_NMANAGER_VPRD_FRAME_SIZE_2_LEN           13
#define VPC_CVDR_REG_NMANAGER_VPRD_FRAME_SIZE_2_OFFSET        0

#define VPC_CVDR_REG_NMANAGER_VPRD_AXI_FRAME_START_2_LEN    30
#define VPC_CVDR_REG_NMANAGER_VPRD_AXI_FRAME_START_2_OFFSET 2

#define VPC_CVDR_REG_NMANAGER_VPRD_LINE_WRAP_2_LEN      13
#define VPC_CVDR_REG_NMANAGER_VPRD_LINE_WRAP_2_OFFSET   16
#define VPC_CVDR_REG_NMANAGER_VPRD_LINE_STRIDE_2_LEN    10
#define VPC_CVDR_REG_NMANAGER_VPRD_LINE_STRIDE_2_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_VPRD_PREFETCH_BYPASS_2_LEN                      1
#define VPC_CVDR_REG_NMANAGER_VPRD_PREFETCH_BYPASS_2_OFFSET                   31
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_2_LEN                                1
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_2_OFFSET                             25
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_OK_2_LEN                             1
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_OK_2_OFFSET                          24
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_ENABLE_PRESSURE_2_LEN                1
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_ENABLE_PRESSURE_2_OFFSET             18
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_ENABLE_FLUX_CTRL_2_LEN               1
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_ENABLE_FLUX_CTRL_2_OFFSET            17
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_ENABLE_DU_THRESHOLD_REACHED_2_LEN    1
#define VPC_CVDR_REG_NMANAGER_VP_RD_STOP_ENABLE_DU_THRESHOLD_REACHED_2_OFFSET 16

#define VPC_CVDR_REG_NMANAGER_VP_RD_DEBUG_2_LEN    32
#define VPC_CVDR_REG_NMANAGER_VP_RD_DEBUG_2_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_RELOAD_0_LEN    4
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_RELOAD_0_OFFSET 24
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_3_0_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_3_0_OFFSET      12
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_2_0_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_2_0_OFFSET      8
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_1_0_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_1_0_OFFSET      4
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_0_0_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_0_0_OFFSET      0

#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_RELOAD_1_LEN    4
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_RELOAD_1_OFFSET 24
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_3_1_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_3_1_OFFSET      12
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_2_1_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_2_1_OFFSET      8
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_1_1_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_1_1_OFFSET      4
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_0_1_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_0_1_OFFSET      0

#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_RELOAD_2_LEN    4
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_RELOAD_2_OFFSET 24
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_3_2_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_3_2_OFFSET      12
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_2_2_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_2_2_OFFSET      8
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_1_2_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_1_2_OFFSET      4
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_0_2_LEN         4
#define VPC_CVDR_REG_NMANAGER_VPRD_ACCESS_LIMITER_0_2_OFFSET      0

#define VPC_CVDR_REG_NMANAGER_SPARE_0_LEN    32
#define VPC_CVDR_REG_NMANAGER_SPARE_0_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_SPARE_1_LEN    32
#define VPC_CVDR_REG_NMANAGER_SPARE_1_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_SPARE_2_LEN    32
#define VPC_CVDR_REG_NMANAGER_SPARE_2_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_SPARE_3_LEN    32
#define VPC_CVDR_REG_NMANAGER_SPARE_3_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_VP_WR_DEBUG_0_LEN    32
#define VPC_CVDR_REG_NMANAGER_VP_WR_DEBUG_0_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_VP_WR_DEBUG_1_LEN    32
#define VPC_CVDR_REG_NMANAGER_VP_WR_DEBUG_1_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_VP_WR_DEBUG_2_LEN    32
#define VPC_CVDR_REG_NMANAGER_VP_WR_DEBUG_2_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_VP_WR_DEBUG_3_LEN    32
#define VPC_CVDR_REG_NMANAGER_VP_WR_DEBUG_3_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_VP_WR_DEBUG_4_LEN    32
#define VPC_CVDR_REG_NMANAGER_VP_WR_DEBUG_4_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_DEBUG_0_LEN    32
#define VPC_CVDR_REG_NMANAGER_DEBUG_0_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_DEBUG_1_LEN    32
#define VPC_CVDR_REG_NMANAGER_DEBUG_1_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_DEBUG_2_LEN    32
#define VPC_CVDR_REG_NMANAGER_DEBUG_2_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_DEBUG_3_LEN    32
#define VPC_CVDR_REG_NMANAGER_DEBUG_3_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_DEBUG_4_LEN    32
#define VPC_CVDR_REG_NMANAGER_DEBUG_4_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_DEBUG_5_LEN    32
#define VPC_CVDR_REG_NMANAGER_DEBUG_5_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_DEBUG_6_LEN    32
#define VPC_CVDR_REG_NMANAGER_DEBUG_6_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_DEBUG_7_LEN    32
#define VPC_CVDR_REG_NMANAGER_DEBUG_7_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_DEBUG_8_LEN    32
#define VPC_CVDR_REG_NMANAGER_DEBUG_8_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_DEBUG_9_LEN    32
#define VPC_CVDR_REG_NMANAGER_DEBUG_9_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_DEBUG_10_LEN    32
#define VPC_CVDR_REG_NMANAGER_DEBUG_10_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_DEBUG_11_LEN    32
#define VPC_CVDR_REG_NMANAGER_DEBUG_11_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_DEBUG_12_LEN    32
#define VPC_CVDR_REG_NMANAGER_DEBUG_12_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_DEBUG_13_LEN    32
#define VPC_CVDR_REG_NMANAGER_DEBUG_13_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_DEBUG_14_LEN    32
#define VPC_CVDR_REG_NMANAGER_DEBUG_14_OFFSET 0

#define VPC_CVDR_REG_NMANAGER_DEBUG_15_LEN    32
#define VPC_CVDR_REG_NMANAGER_DEBUG_15_OFFSET 0

#endif // __VPC_CVDR_REG_NMANAGER_REG_OFFSET_FIELD_H__
